——簡化的RISC CPU設(shè)計(jì)

咱們討論簡化的RISC CPU設(shè)計(jì)。

2.RISC CPU結(jié)構(gòu)

④算數(shù)運(yùn)算器

算術(shù)邏輯運(yùn)算單元 根據(jù)輸入的8種不同操作碼分別實(shí)現(xiàn)相應(yīng)的加、與、異或、跳轉(zhuǎn)等8種基本操作運(yùn)算。利用這幾種基本運(yùn)算可以實(shí)現(xiàn)很多種其它運(yùn)算以及邏輯判斷等操作。

其VerilogHDL 程序見下面的模塊：

//------------------------------------------

module alu (alu_out, zero, data, accum, alu_clk, opcode);

output [7:0]alu_out;

output zero;

input [7:0] data, accum;

input [2:0] opcode;

input alu_clk;

reg [7:0] alu_out;

parameter HLT =3’b000,

SKZ =3’b001,

ADD =3’b010,

ANDD =3’b011,

XORR =3’b100,

LDA =3’b101,

STO =3’b110,

JMP =3’b111;

assign zero = !accum;

always @(posedgealu_clk)

begin //操作碼來自指令寄存器的輸出opc_iaddr<15..0>的低3位

casex (opcode)

HLT: alu_out<=accum;

SKZ: alu_out<=accum;

ADD: alu_out<=data+accum;

ANDD: alu_out<=data&accum;

XORR: alu_out<=data^accum;

LDA: alu_out<=data;

STO: alu_out<=accum;

JMP: alu_out<=accum;

default: alu_out<=8'bxxxx_xxxx;

endcase

end

endmodule

//------------------------------------------