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The TPS3619 and TPS3620 families of supervisory circuits monitor and control processor activity by providing backup-battery switchover for data retention of CMOS RAM.
During power on, RESET is asserted when the supply voltage (VDD or VBAT) becomes higher than 1.1 V. Thereafter, the supply voltage supervisor monitors VDD and keeps RESET output active as long as VDD remains below the threshold voltage (VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time starts after VDD has risen above VIT. When the supply voltage drops below VIT, the output becomes active (low) again.
The product spectrum is designed for supply voltages of 3.3 V and 5 V.
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