如何相移可以幫助改善性能的DC / DC轉(zhuǎn)換器

　　?，F(xiàn)代電子系統(tǒng)板的集成電路如FPGA，DSP，微處理器，存儲(chǔ)器和ASIC芯片。此外，還有音頻放大器和射頻功率放大器模塊板上與聲音和無(wú)線(xiàn)通信。這種電路板上的每個(gè)器件或模塊對(duì)電壓和電流有不同的要求。因此，在分布式電源架構(gòu)，這些半導(dǎo)體器件和模塊是由多種負(fù)荷切換點(diǎn)（POL）供電的直流/直流轉(zhuǎn)換器，獲得他們的輸入從一個(gè)共同的總線(xiàn)電壓以產(chǎn)生所需的電壓或電壓的半導(dǎo)體集成電路和模塊。

　　從一個(gè)單一的源產(chǎn)生一系列的調(diào)節(jié)直流輸出電壓施加高均方根（RMS）電流紋波和噪聲問(wèn)題的直流輸入源。為了解決噪聲問(wèn)題，設(shè)計(jì)師通常使用額外的成本輸入濾波。由于每個(gè)開(kāi)關(guān)轉(zhuǎn)換器使用不同的開(kāi)關(guān)頻率，拍頻100赫茲和23千赫之間產(chǎn)生的，它可以降低系統(tǒng)音頻放大器的性能。

　　Recently， Intersil published a white paper1 describing how the input RMS current ripple and noise can be minimized by preventing the on-time overlapping of these multiple， on-board DC/DC converters using phase-shifting techniques. In reality， this technique also improves EMI and eliminates the need for input filtering， while tackling the problems linked with beat frequencies.

　　This article examines how multiple DC/DC buck regulators are organized in a master/slave configuration using phase-shifting time delays to improve the noise performance on the source input of these on-board DC/DC converters. It also demonstrates the implementation of the phase-shifting time delay technique using Intersil’s synchronous buck regulator ISL8018， which is tailored for this design. In addition， by synchronizing multiple DC/DC converters using the same clock， the article also shows that beat-frequency problems can be eliminated from the system.