使用 VHDL 語言實現(xiàn)MC68360 微處理器和SDRAM 之間的接口控制電路，為摩托羅拉68xxx CPU在開發(fā)設(shè)計中使用SDRAM 提供一種靈活，高效，可靠的解決方案。文中提到的接口電路設(shè)計有別于其他IP 核的SDRAM 控制器，只要簡單理解計算機(jī)系統(tǒng)中片選信號，讀寫信號、時鐘及數(shù)據(jù)和地址總線的含義就可以實現(xiàn)對SDRAM 的多種方式的操作。可以廣泛適用于時鐘在5MHz 以上任何一種通用的微處理器和SDRAM 接口設(shè)計應(yīng)用中。并在實踐中得到廣泛應(yīng)用。
關(guān)鍵詞：SDRAM MC68360 VHDL
The Interface of design between MC68360 and SDRAM Liu Hao1，Ji Lixin2，Wang Fuyuan1, Hang Dequan2 (1：College of Information Engineering, ZhengZhou University, Zhengzhou 450001；2：National Digital Switching System Engineering & Technological R&D Cente (NDSC),Zhenghzou 450002) 【Abstract】 It describes a new interface-control methodology to implement an interface between MC68369 and SDRAM with VHDL which provides a flexible、reliable and efficient solution in Design with Motorola 68xxx CPU. The difference between this interface circuit in this paper and other IP SDRAM controller is to manipulate SDRAM easily ,and do not need to be familiar with any specific computer system. It only need to know about Chip select, Read or Write signals, Address Bus, Data Bus, SDRAM . It can be used widely in many kinds of microcomputer system which clock frequency is 5MHz and more.
【Key words】：SDRAM MC68360 VHDL