給出了一種基于FPGA 的等占空比任意整數(shù)分頻電路的設(shè)計(jì)方法。首先簡(jiǎn)要介紹了FPGA 器件的特點(diǎn)和應(yīng)用范圍, 接著討論了一些常見整數(shù)分頻的方法, 而本文運(yùn)用一種新的可控分頻器設(shè)計(jì)方法——脈沖周期剔除法, 主要是對(duì)半周期進(jìn)行計(jì)數(shù), 配合時(shí)鐘反相電路, 可以實(shí)現(xiàn)占空比50% 的任意整數(shù)分頻, 分頻系數(shù)由控制端給定。本設(shè)計(jì)在M ax+ P lusê開發(fā)軟件下, 利用VHDL 硬件描述語(yǔ)言和原理圖輸入方式, 可以方便地實(shí)現(xiàn)分頻器電路的設(shè)計(jì)。在文中給出了N = 3 時(shí)分頻電路設(shè)計(jì), 并對(duì)電路進(jìn)行了仿真和測(cè)試, 實(shí)驗(yàn)結(jié)果符合設(shè)計(jì)要求。
Th is paper gives out a design of the equal duty rat io arbit rary integer frequency divider based on FPGA 1 F irst int roduces the characterist ics and app licat ion domain of FPGA in brief1 Then discusses a few t radit ional integer frequency dividers1 But th is paper p resents a new concep t of p rogrammable frequency divider1A n algo rithm based on the new concep t is int roduced also1U sing th is method can realize 50% duty rat io integral frequency division1 The frequency division coefficient is given by cont ro l end1 The frequency divider is described in VHDL , and synthesized, simulated w ithM ax+ P lusê foundat ion1L ast, the N = 3 design p ract ice based on the algo rithm is given, the experimental results show that the perfo rmance has confo rm to the p ropo sed algo rithm1