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標(biāo)簽 > design
design,中文是設(shè)計(jì)之意,即“設(shè)想和計(jì)劃,設(shè)想是目的,計(jì)劃是過程安排”,通常指有目標(biāo)和計(jì)劃的創(chuàng)作行為、活動(dòng)。在這個(gè)競(jìng)爭(zhēng)激烈的數(shù)字化信息時(shí)代,企業(yè)建立自己的網(wǎng)站已經(jīng)刻不容緩。
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Sustain a Design with the DS2409 MicroLAN Coupler
The DS2409 is designed for use in access-control probe points (i.e., readers...
Reference Design for a Class-D
Abstract: This reference design demonstrates the use of the MAX9736 Class D ...
2009-05-05 標(biāo)簽:Design 2008 0
“一站式” PCB 設(shè)計(jì) 第一期:課程總覽及 Allegro X Design Platform 24.1 新功能
回放視頻包含完整課程和demo演示;視頻節(jié)點(diǎn)和課程內(nèi)容如下表所示?,F(xiàn)場(chǎng)問答已精簡(jiǎn)、整理為文字版并收錄在課件PPT中,方便大家快速查閱。直播問答整理如下,...
2024-11-02 標(biāo)簽:PCB設(shè)計(jì)allegrodesign 1999 0
2024年度網(wǎng)課 I “一站式” PCB 設(shè)計(jì)——基于 Allegro X Design Platform 24.1 最新版本
PCB設(shè)計(jì)是一門綜合學(xué)科,包括硬件、結(jié)構(gòu)、工藝、信號(hào)完整性……這些領(lǐng)域需要緊密配合。每個(gè)行業(yè)、公司都有其獨(dú)特的PCB設(shè)計(jì)需求。但是,無縫協(xié)同、數(shù)據(jù)可視可...
2024-10-12 標(biāo)簽:PCB設(shè)計(jì)allegrodesign 1964 0
Allegro X Design Platform多人協(xié)同團(tuán)隊(duì)設(shè)計(jì)功能操作演示及講解
CadenceAllegroX設(shè)計(jì)平臺(tái)是一個(gè)強(qiáng)大而統(tǒng)一的系統(tǒng)設(shè)計(jì)解決方案,可促進(jìn)基于團(tuán)隊(duì)的協(xié)作環(huán)境,以支持尖端和現(xiàn)代化的電子設(shè)計(jì)需求。SymphonyT...
Robust Contact Monitor Simplif
Abstract: This application note demonstrates how the MAX13362 automotive swi...
汽車壓力傳感器的設(shè)計(jì)與制造--Design and Manu
Abstract: Design and manufacturing methodologies for automotive pressure sen...
2009-04-20 標(biāo)簽:Design 1528 0
DS1875 Trends in High-Performa
Trends in High-Performance Power-Supply Design for Automotive Infotainment ...
2008-12-16 標(biāo)簽:Design 1442 0
Design Guidelines for High-Per
Abstract: This application note will help the designer of a high-performance...
Transmitter Reference Design f
Transmitter Reference Design for a 900MHz Full-Duplex Radio Abstract: This...
2008-08-18 標(biāo)簽:Design 1141 0
Interfacing User Devices and t
Abstract: This application note shows how one can access the DST1E1DK via th...
AMD Vivado Design Suite 2024.2全新推出
AMD Vivado Design Suite 2024.2 全新推出,使用 AMD Versal Adaptive SoC 進(jìn)行設(shè)計(jì)的重大改進(jìn)。此版本...
QuickChip Design Example 1 - A
Abstract: A broadband phase-lock loop (PLL) building block integrated circui...
2009-04-20 標(biāo)簽:Design 1006 0
Design Considerations for Data
Abstract: The requirements for interconnect between computers, cell phones o...
2009-04-24 標(biāo)簽:Design 991 0
Design Challenges for an Ultra
Design Challenges for an Ultra-Low-Jitter Clock Synthesizer Abstract: ...
2008-12-25 標(biāo)簽:Design 985 0
Design Considerations for Dall
Abstract: A real-time clock (RTC) allows a system to synchronize or time-sta...
2009-04-17 標(biāo)簽:Design 968 0
Robust Contact Monitor Simplif
Abstract: This application note demonstrates how the MAX13362 automotive swi...
Designing the DS2726 to Protec
Designing the DS2726 to Protect Li+ Batteries During a Reverse Charger Event...
2008-12-18 標(biāo)簽:Design 928 0
Ratiometric Design Overcomes t
Abstract: This application note explains how to eliminate the voltage change...
2009-04-20 標(biāo)簽:Design 727 0
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